|Title||Static Timing Analysis (STA) – Bangalore – 3-5yrs Exp – Salary As per Industry standards|
|Salary||As per Industry Standards|
|Total Yrs Of Experience Required||3-5yrs|
Synthesis and STA
Placement/Power aware synthesis using Synopsys & Cadence tools (DCG/NXT/FC, Genus)
• Constraints development, Formal Verification, Static Timing Analysis & timing closure
• Work closely with physical design team, design team and other cross-functional teams
• 3 to 5 years of experience in synthesis, STA and timing closure
• Exposure to safety protocols
• Proficiency with Synopsys DC & PT tools and Verilog/VHDL is a must
• Good knowledge of IO interfaces like DDR is preferred
• Experience in Perl, TCL and shell scripting is desirable
High-speed and Low-power area optimized hardmacro implementation •Primary tasks include writing timing constraints, synthesis, formal verification, CLP, Primetime, PTPX, Func and timing ECO •Optimize datapath design for low-area, low-power and high-speed using advanced features in synthesis such as MCMM, SAIF, multibit mapping etc.
•Optimize PPA using the right tool options and stdcell libraries / memories •Handle complex digital blocks with 1M-5M gates in advanced FinFET process nodes.
•This candidate will work closely with RTL, DFT and PD teams to converge on area, timing, power and testability to close timing in sub-micron technologies (from 28nm to 10nm).
•Should be able to work on netlist level ECOs manually or with conformal ECO tool.
•The candidate should also possess automation skills and be well versed in scripting languages (perl, TCL, shell, python) •Strong communication skills to work with design teams worldwide, good team player and be a self-starter