Job: Layout Design Engineer-Semiconductor-Bangalore-3-7yrs+-Market stds

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Title Layout Design Engineer-Semiconductor-Bangalore-3-7yrs+-Market stds
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Categories IT Jobs
Salary Market standards
Total Yrs Of Experience Required 3-7yrs
Job Location Bangalore
Job Description

Our client is a fabless semiconductor company innovating high performance IC products for IoT Radios, Timing and Portable Audio markets located in Bangalore.

Our client is looking for “Layout Design Engineer” for Bangalore location.

  • Exp : 3-7 yrs
  • JD attached
  • No of positions – 3

Job Description

Layout Design Engineer – (Analog/RF) Junior/Senior

• Job Overview Duties include
• As a Layout design engineer (Analog/RF), you will be responsible to perform IC mask layout design and physical verification of Custom analog/RF mixed signal, IO & ESD designs and Block/Module level.
• You will be responsible for executing the layout, lvs/drc/antenna checks on complex custom analog/RF mixed-signal integrated circuits.
• You will work very closely with circuit designers and CAD engineers to perform custom analog mixed-signal blocks layout.
• Adherence and maintenance of already established companywide layout design & CAD methodologies and process flows.

ESSENTIAL FUNCTIONS
• Provide IC Layout Design support by performing Custom floor planning, custom routing and physical verification of analog/RF mixed-signal block or macro levels, IOs or IO ring layout designs.
• Perform layout verification with LVS/DRC/Antenna support, quality check and documentation.
• Ability to work and communicate effectively in a team and to be able to multi-task effectively in a fast-paced work environment.
• Must recognize failure prone circuit and layout structures, dedicatedly work with circuit designer for best approach to problems

REQUIREMENTS
• Candidates preferred from premier institutes for fresher and all experience levels
• A technology-related Bachelor’s degree with 3-7 years of related experience for senior positions.
• Prepare Transistor level floorplan in a multi-voltage, mixed-signal, high speed and noise-sensitive environment.
• Experience with Cadence Virtuoso-XL and Virtuoso-L, Mentor Graphic Calibre, Cadence Assura/PVS and Linux Operating System.
• High level proficiency in interpretation of calibre/Assura DRC, LVS, ERC, antenna and post layout extraction.
• Must have good understanding of analog layout techniques (Device matching, shielding, LOD/STI, WPE, PSE, OSE, RF Concepts, minimizing parasitics and high power routing etc.)
• Must have good understanding of CMOS fabrication concepts and process.
• Must have good verbal and written communication skills and experienced in creating documents using Microsoft Office and Microsoft Power Point.
• Strong knowledge of Latch up prevention and ESD protection schemes a plus.
• You understand issues of RC delay, electro migration, and cross capacitance
• Good knowledge of skill, Perl , C-shell and TCL programming to be able to automate repeatable tasks for productivity improvements in layout a plus.
• Good knowledge of understanding the calibre/Assura drc/lvs/antenna etc rule decks and able to customize the rules a plus
• Understanding and driving methodology improvements in layout for productivity improvement.
• Target companies (TI, ADI, Broadcom, MaxLinear, NXP, Qualcomm, Microchip, Cypress, etc

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