|Title||GLS Verification Engineer – 3+yrs – Bangalore – Salary As per Industry Standards|
|Salary||As per Industry Standards|
|Total Yrs Of Experience Required||3+yrs|
Job Description: DV engineer with good expertise in SV/UVM concepts.
Understanding of DDR protocols preferred.
Good debugging and communication skills.
Release Comments: Please share profiles with some domain experience in LPDDR4, LPDDR5 kind of technologies
Design verification of next generation QDSP cores, candidate should be skilled SV/UVM, CPU micro-architecture, AXI/similar bus protocols, hands on experience with testbench development, debug and regression management.
Responsible for building and maintaining GLS testbench (SV/UVM).
Responsible for generating constrained random tests for the DSP core and verify the Core netlists with and without timing.
Responsible for verifying Power aware correctness in the netlist through PAGLS.
Implement and deploy new verification methodologies, automation to continuously improve quality and efficiency .