|Title||Verification engineer – 6years to 12years – Bangalore – Salary : Best in the Industry|
|Salary||Best in the Industry|
|Total Yrs Of Experience Required||6years to 12years|
Job Description :
Responsible for building and maintaining GLS testbench (SV/UVM).
Responsible for generating constrained random tests for the DSP core and verify the Core netlists with and without timing.
Responsible for verifying Power aware correctness in the netlist through PAGLS.
Implement and deploy new verification methodologies, automation to continuously improve quality and efficiency
DV engineer with good expertise in SV/UVM concepts.
Understanding of DDR protocols preferred.
Good debugging and communication skills.
Design verification of next generation QDSP cores, candidate should be skilled SV/UVM, CPU micro-architecture, AXI/similar bus protocols, hands on experience with testbench development, debug and regression management.