Job: Sub-system verification,system verilog, UVM,4-10 years, 15-20 Lakhs,Bangalore,Immediate joiners

o   Should have 4 yrs to 10 yrs experience

o   SV UVM experience

o   Defining verification strategy, architecting testbench

o   Independently developed a testbench from scratch

o   Experience of complete verification cycle in more than one project

o   Ability to guide junior resources

o   Good presentation skill

Candidates who can join immediately or within 30 days are preferred.