Job: SUb system verification, UVM, System verilog, 8-12years, Bangalore, Best in industry, Notice period max 30 days

 SV UVM experience
– Defining verification strategy, architecting testbench 

– Independently developed a testbench from scratch 

– Experience of complete verification cycle in more than one project
– Ability to guide junior resources
– Good presentation skills
–Perl or Python scripting experience
Exp – 8 to 12 years 

We need people who can join in max of 4 weeks.