Job: DDR verification,System verilog,ASIC engineer,UVM, 5+ years, Noida, Immediate joiners

Title	DDR verification,System verilog,ASIC engineer,UVM, 5+ years, Noida, Immediate joiners
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Categories	Embedded Jobs
Salary	As per industry standards
Total Yrs Of Experience Required	5-10
Job Location	Noida
Job Description	o Experienced ASIC Verification engineer responsible for implementing and executing verification plan to verify DDR memory Controller/PHY features. o Requires a strong background in digital verification from planning to coverage closure. o Previous experience designing configurable IP is a strong plus. o 5+ Years of experience in verification using SV/UVM at IP level. o Desired skills o Knowledge of DDR memory protocol o Knowledge of Python or Perl for scripting o Experience with highly configurable designs Candidates who can join immediately or within 30 days are preferred.
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