o Experienced ASIC Verification engineer responsible for implementing and executing verification plan to verify DDR memory Controller/PHY features.
o Requires a strong background in digital verification from planning to coverage closure.
o Previous experience designing configurable IP is a strong plus.
o 5+ Years of experience in verification using SV/UVM at IP level.
o Desired skills
o Knowledge of DDR memory protocol
o Knowledge of Python or Perl for scripting
o Experience with highly configurable designs