|Title||ASIC RTL Engineer – 1 to 5yrs Exp – Bangalore – Salary As per Industry Standards|
|Total Yrs Of Experience Required||1-5yrs|
We have a new requirement for ASIC RTL.
Mandatory work – CDC, Lint
Location – Bangalore
Exp range – 1 to 3 years & 3 to 5 years.
Notice period should be less than 30 days.
Job Description: Must have hands on experience with design and integration of complex multi clock domain blocks Experience in Verilog/System-Verilog is a must.
Should have knowledge of AMBA protocols – AXI, AHB, APB, clocking/reset/debug architecture Hands on experience in Multi Clock designs, Asynchronous interface is a must.
Work closely with the Design verification and validation teams for pre/post Silicon debug Experience in Synthesis / Understanding of timing concepts for ASIC is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required.